1. Field of the Invention
Embodiments of the present invention are related to semiconductor memory devices. In particular, embodiments of the invention are related to a phase change memory device and a program method thereof.
A claim of priority is made to Korean Patent Application No. 2005-86619, filed Sep. 16, 2005, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
Integrated circuit memory devices are typically classified into one of two categories. These categories include random access memory (RAM) and read only memory (ROM) devices. Random access memory devices are typically volatile memory devices that lose their data when power to the memory is interrupted. In contrast, read only memory devices are typically non-volatile memory devices that retain their data even in the presence of power interruption. Examples of random access memory devices include dynamic RAM (DRAM) and static RAM (SRAM). Examples of non-volatile memory devices include programmable ROM (PROM), erasable programmable ROM (EPROM) and electrically erasable programmable ROM (EEPROM).
Recently, semiconductor memory devices have been introduced which utilized various non-volatile materials intended to replace the capacitive element of a conventional DRAM cell. Examples of these devices include ferroelectric RAM (FRAM) devices having ferroelectric capacitors, magnetic RAM (MRAM) devices having tunneling magneto-resistive (TMR) films, and a phase change memory (PRAM) devices having chalcogenide alloys. Among these, the phase change memory devices have garnered substantial attention due to their large memory capacity, ease of manufacture, and relatively low cost.
The phase-change random access memory (PRAM), also known as an Ovonic Unified Memory (OUM), includes a phase-change material such as a chalcogenide alloy which is responsive to heat so as to be stably transformed between crystalline and amorphous states. Such a PRAM is disclosed, for example, in U.S. Pat. Nos. 6,487,113 and 6,480,438.
The phase-change material of the PRAM exhibits a relatively low resistance in its crystalline state, and a relatively high resistance in its amorphous state. In conventional nomenclature, the low-resistance crystalline state is referred to a ‘set’ state and is designated logic “0”, while the high-resistance amorphous state is referred to as a ‘reset’ state and is designated logic “1”.
The terms “crystalline” and “amorphous” are relative terms in the context of phase-change materials. That is, when a phase-change memory cell is said to be in its crystalline state, one skilled in the art will understand that the phase-change material of the cell has a more well-ordered crystalline structure when compared to its amorphous state. A phase-change memory cell in its crystalline state need not be fully crystalline, and a phase-change memory cell in its amorphous state need not be fully amorphous.
Generally, the phase-change material of a PRAM is reset to an amorphous state by heating the material in excess of its melting point temperature for a relatively short period of time. On the other hand, the phase-change material is set to a crystalline state by heating the material below its melting point temperature for a longer period of time. In each case, the material is allowed to quickly cool to its original temperature after the heat treatment.
The speed and stability of the phase-change characteristics of the phase-change material are critical to the performance characteristics of the PRAM. As suggested above, chalcogenide alloys have been found to have suitable phase-change characteristics, and in particular, a compound including germanium (Ge), antimony (Sb) and tellurium (Te) (e.g., Ge2Sb2Te5 or GST) exhibits a stable and high speed transformation between amorphous and crystalline states.
FIG. 1 is an equivalent circuit diagram of a phase change memory cell. As shown, the memory cell 10 includes a variable resistor C and a transistor M connected in series between a bit line BL and a reference potential (e.g., ground), with a gate of the transistor M being connected to a word line WL. The variable resistor C includes a phase-change material which, as described above, is programmed between crystalline and amorphous states.
The set and reset states of the memory cell 10 of FIG. 1 are established by controlling the magnitude and duration of current flow through the variable resistor C. The variable resistor C is activated (or accessed) by operation of the transistor M which is responsive to a voltage of the word line WL. When activated, the memory cell 10 is programmed according to the voltage of the bit line BL. That is, the bit line BL voltage is controlled to establish a programming current which selectively programs the variable in its ‘set’ and ‘reset’ states.
FIG. 2 illustrates an example of temperature pulse characteristics of a phase-change material as the phase-change material is programmed in the ‘set’ and ‘reset’ states. In particular, reference number 1 denotes the temperature pulse of the phase-change material programmed to its ‘reset’ state, and reference number 2 denotes the temperature pulse of the phase-change material programmed to its ‘set’ state.
As shown in FIG. 2, when the phase-change material is programmed to its ‘reset’ state, the temperature of the material is increased above its melting temperature Tm (e.g., 610° C.) for a relatively short period of time, and then allowed to rapidly cool. In contrast, when the phase-change material is programmed to its ‘set’ state, the temperature of the material is increased to below its melting point Tm and above its crystallizing temperature Tc (e.g., 450° C.) for a longer period of time, and then allowed to cool more slowly. The fast and slow cooling of the ‘reset’ and ‘set’ programming operations are referred to in the art as fast “quenching” and slow “quenching”, respectively. The temperature range between the melting temperature Tm and the crystallizing temperature Tc is referred to as the “set window”.
It should be noted that the phase-change memory cell 10 of FIG. 1 is presented as an example only, and that other structures may be possible. For example, the memory cell 10 may instead include the variable resistor and a diode connected in series between the bit line BL and the word line WL.
A write driver of the phase change memory device is used to provide the programming current discussed above, i.e., to provide a ‘set’ current or ‘reset’ current to the bit line of the phase change memory cell being programmed. As with other types of non-volatile memory devices, there is a general demand in the industry to reduce the operational voltages of power supply circuits contained in phase change memory devices. However, as the supply voltage of the phase change memory device is reduced (e.g., from 2.5V to 1.8V), it become increasingly difficult for the write driver to generate sufficient write currents to reliably program the phase change memory cells into the ‘set’ and ‘reset’ states. As such, it has been suggested to use a voltage pump circuit in conjunction with the write driver in an effort to ensure adequate write currents during programming. Unfortunately, however, the conventional solutions employing a voltage pump circuit can substantially slow the overall programming operation.